1. Field of the Invention
The invention relates to a method for making very low threshold voltage (Vt) metal-gate/high-κ CMOSFETs. More particularly, the invention relates to a method for making very Low Vt [Ir—Hf]/HfLaO CMOS using self-aligned low temperature shallow junctions with gate-first process compatible with VLSI fabrication process.
2. Description of the Related Art
The undesired high Vt at small equivalent-oxide thickness (EOT) is the major technology challenge for metal-gate/high-κ CMOSFETs, while the detailed mechanisms are still not clear yet [1]*-[6]* (please refer to table 1 for detail prior arts [1]*-[6]* listed in Summary of the Invention). One method to address this issue is to compensate the high Vt by using proper dual metal-gates, which have an effective work-function (φm-eff) lower than the target 4.1 eV for n-MOS, and higher than the needed 5.2 eV for p-MOS. Although low-temperature-formed fully-silicidation (FUSI) of Lanthanide-silicide (YbxSi) [2]* and TaC gates work well for n-MOS, the choice of an appropriate metal gate for p-MOS is especially difficult. This is because only Pt and Ir in the Periodic Table have a required work-function greater than the target 5.2 eV [2]*, but Pt is difficult to be etched by RIE. Previously, it is showed that Ir3Si/HfLaON p-MOS [1]* has the needed high φm-eff of 5.08 eV and low Vt of −0.1 V at 1.6 nm EOT, even after ion implant activation of a 1000° C. RTA. Unfortunately, further scaling EOT to 1.2 nm, reduces flat-band voltage (Vfb) of these devices to produce an undesirable high Vt. Since this approach was not successful, a fundamental understanding of the high Vt and Vfb roll-off is necessary, when EOT is scaled.